内建式自我测试(BuiltInSelfTest,BIST)为超大型积体电路常用的测试.doc

Problem A1: Test Pattern Generation by Using Reseedable LFSRs Abstract Built-In-Selft-Test (BIST) is one of most popular test solutions to test the embedded cores in a chip. The BIST circuit can generate pseudo random test patterns to test these embedded cores without using expensive Automatic Test Equipments (ATEs). On the other way, if you have test vectors which are generated by the test generator, you can design a pseudo random pattern generator suitable for hitting these test vectors in short time. In this subject, try to write a program to create the pseudo random pattern generator, performed by Linear Feedback Shift Registers (LFSRs), for hitting the generated test vectors. The output of LFSRs can be rearranged before feeding to the input of Core Under Test (CUT). The lengths of LFSRs and the numbers of LFSRs are no limit. In the vectors generation procedure, the seeds of LFSRs can be changed for the purpose of saving BIST time. 1. Introduction: Linear Feedback Shift Registers (LFSRs) are widely adopted as the pseudo-random test pattern generators for built-in self test (BIST) of logic circuits shown in Figure1, due to its low hardware overhead. However, there are many faults in the circuits under test (CUTs) that are hardly detected by the test patterns generated by using the traditional LFSRs, certain deterministic patterns are needed for achieved higher fault coverage. These extra patterns can be stored in the memory of an external tester or the on-chip memory. In order to reduce the time of LFSR to generate patterns for testing such hard to detect fault, storage requirements, one of the solutions is to change seeds of the LFSRs during test pattern generation. A seed refers to the initial state of an LFSR. The procedure for changing the seed of the LFSR is called reseeding. Since the seeds still need to be stored in the memory, it needs a good reseeding strategy to reduce a large test data volume into a smaller set of seeds. Figure 1: BIST Architectur