采用图划分技术的多端口RC网络约减方法.pdfVIP

第 23 卷第 10 期 半 导 体 学 报 Vol . 23, No . 10 2002 年 10 月 C~INESE JOURNAL OF SEMICONDUCTORS Oct ================================================================= . , 2002 % Project supported by National Natural Science Foundation of China ( No . and State Key Development Propram for Basic Research of China ( No . G 1999032903D Yang ~uazhong male , Was born in 1967, professor . ~is research f ield covers speech / audio signal processing chips , CMOS analog and RF integrated circuits , system - on - a - chip architectures , and their design automation technigues . Mao Xiaoj ian male , Was born in 1978, PhD candidate . ~is research interests are in CMOS RF IC design and design automation . Yan Zhaoran male , Was born in 1978, MS candidate . ~e mainly focuses on static timing analysis and reduced modeling . Received 1 February 2002, revised manuscript received 25 April 2002 0 c 2002 The Chinese Institute of Electronics A Reduced - Order modeling of multi - Port RC networks by means of graph Partitioning % Yang ~uazhong , Mao Xiaoj ian , Yan Zhaoran and Wang ~ui ( DepaTtment Of E eCtTOniC EngineeTing , Tsing ~a Uni eTsit , Beijing 100084, C ina D Abstract A modif ied reduced - order method for RC netWorks Which takes a division - and - conguest strategy is presented . The Whole netWork is partitioned into a set of sub - netWorks at f irst , then each of them is reduced by Krylov subspace technigues , and f inally all the reduced sub - netWorks are incorporated together . With some accuracy , this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods Which usually only of fer a reduced net With less nodes . This can markedly accelerate the sparse - matriX - based simulators Whose performance is dominated by the entity of the matriX or the number of components of the circuits . ey words interconnect reduced - order modeling graph partitioning Krylov subspace ACC 1130 B 1110 CLC number TN 702 Doc