采用精确时延模型基于路径的缓冲器插入时延优化.pdfVIP

第 卷第 期 半 导 体 学 报 25 5 Vol. 25 No. 5 年 月 2004 5 C~INESE J0 URNAL 0 F SEMIC0 NDUCT0 RS May 2004 ================================================================= Path-Based timing optimization by Buffer Insertion with Accurate Delay model% Zhang Yigian Zhou Giang ~ong Xianlong and Cai Yici ( DepeTtment of CompUteT S6ien6e Te6hnology TsinghUa uniUeTsity Beijing 100084 China) Abstract; An algorithm of path-based timing optimiZation by buffer insertion is presented. The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look-up table for gate delay estimation. And heuristic method of buffer insertion is presented to reduce delay. The algorithm is tested by industral circuit case. EXperimental results shoW that the algorithm can optimiZe the timing of circuit efficiently and the timing constraint is satisfied. Key words; buffer insertion; timing optimiZation; interconnect planning; routing algorithm A ; 2570 A ; 7410D number; TN47 Document code; A Article ID; 0253-4177( 2004) 05-0520-06 buffer location. Van Ginneken [6I proposed a 1 Introduction dynamic programming algorithm Which finds the optimal solution under the Elmore Wire delay With progress in VLSI sub-micron model and a linear gate delay model. Several technology interconnect delay has become a variants of this algorithm have been proposed[1 7 8I . dominant factor in integrated circuits. Interconnect These algorithms