Design of DC-DC Converter for Flash Memory IPs.docVIP

Engineering, 2013, 5, 142-145 doi:10.4236/eng.2013.51b026 Published Online January 2013 (http://www.SciRP.org/journal/eng) Design of DC-DC Converter for Flash Memory IPs Liyan Jin, Woo-Young Jung, Ji-Hye Jang, Min-Sung Kim, Myeong-Seok Kim, Heon Park, Pan-Bong Ha, Young-Hee Kim Department of electronic engineering, Chanwon National University, Changwon , South Korea Email: youngkim@changwon.ac.kr, pha@changwon.ac.kr Received 2013 Abstract A DC-DC converter for flash memory IPs performing erasing by the FN (Fowler-Nordheim) tunneling and program- ming by the CHEI (channel hot electron injection) is designed in this paper. For the DC-DC converter for flash memory IPs using a dual voltage of VDD (=1.5V±0.15V)/VRD (=3.1V±0.1V), a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD (=3.1V±0.1V) is a regulated voltage by a voltage regulator with an external voltage of 5V, which is used as the WL activation voltage in the read mode and an input voltage of the charge pump. The designed DC-DC converter outputs positive voltages of VP6V (=6V), VP8V (=8V) and VP9V(=9V); and a negative voltage of VM8V (=-8V) in the write mode. Keywords: Flash memory; CHCI, DC-DC converter, charge pump, low-voltage 1. Introduction As a market for MCU (microcontroller unit) applied products such as mobile devices, household appliances, and so on grows continuously, the need of small-area non-volatile memories is also stressed [1]. As shown in Fig. 1, flash memories are applied to products requiring a memory capacity of more than 1 Mbits as a non-volatile memory [2]. An EEPROM cell of the SSTC (side-wall selective tran- sistor cell) scheme was proposed as a small-area design technology [2]. The SSTC EEPROM cell has a structure that the CG (control gate) surrounds the sides of the FG (floating gate). The conventional EEPROM cell has a