《数字电子技术基础第二版》5.8时序逻辑电路.pptVIP

5.8 用VHDL描述逻时序电路 上页 下页 后退 模拟电子 数字电子技术基础 上页 下页 返回 5.8.1 计数器的VHLD语言描述 十进制计数器的VHDL程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter10 is Port ( clk : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end Counter10; architecture Counter10_Body of Counter10 is signal Count : STD_LOGIC_VECTOR(3 downto 0); begin Counter10_Proc: process(clk) begin if clkevent and clk =1 then if Count1001 then Count=Count+1; else Count=0000; end if; end if; end process; Q= Count; end Counter10_Body; 5.8.2 信号发生器的VHLD语言描述 LIBBARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY seq IS PORT( start:IN STD_LOGIC; clk:IN STD_LOGIC; data_out:OUT STD_LOGIC_vector(5 DOWNTO 0) ); END seq; 序列信号发生器VHDL程序 AECHITECTURE Behavioral of seq IS SIGNAL TEMP_data_out:STD_LOGIC_vector(5 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF(clk’event and clk=1 THEN IF start=‘1’THEN TEMP_data_out(1)=TEMP_data_out(0); TEMP_data_out(2)=TEMP_data_out(1); TEMP_data_out(3)=TEMP_data_out(2); TEMP_data_out(4)=TEMP_data_out(3); TEMP_data_out(5)=TEMP_data_out(4); TEMP_data_out(0)=TEMP_data_out(5); ELSE TEMP_data_out=“000000”; END IF; END IF; END PROCESS; Data_out=TEMP_data_out; END Behavioral;