I2C_总线入门.pptVIP

2009/01/19 I2C- BUS History History THE I2C-BUS BENEFITS Definition of I2C-bus terminology START and STOP conditions Data transfer on the I2C-bus Acknowledge on the I2C-bus Synchronization(SCL) Arbitration(SDA) Possible data transfer format Possible data transfer format Definition of bits in the first byte * Prepare by Ivan Chuang The Standard-mode I2C-bus specification, with its data transfer rate of up to 100 kbit/s and 7-bit addressing, has been in existence since the beginning of the 1980’s . Many of today’s applications need to transfer large amounts of serial data continuing improvements in semiconductor technologies As most of the 112 addresses available with the 7-bit addressing scheme were soon allocated (? 10 bits address) VER 1.0 –1992 The Fast-mode is added (bit rate up to 400 k bit/s) 10-bit addressing is added (1024 additionalslave addresses) VER 2.0- 1998 The High-speed mode (Hs-mode) is added. (bit rate up to 3.4Mbit/s) The fixed input levels for new devices are replaced by bus voltage-related levels. Application information for bi-directional level shifter is added. VER 2.1-2000 Some timing parameters in Hs-mode have been relaxed Only two bus lines are required(SDA/SCL) Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 k bit/s( Standard) 400 k bit/s ( Fast) 3.4 M bit/s(High-speed) Each device connected to the bus is software addressable by a unique address multi-master bus including collision detection and arbitration to prevent data corruption filtering rejects spikes on the bus data line to preserve data integrity The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF. BUSY FREE TRANSFERRING DATA： 1) START 2) 7-bit Slave address 3) R/nW bit 4) ACK 5) 8bit data 6) ACK/NAK 7) repeat step5 and step6 8) repeat START(step1)or STOP (SDA) (SDA) (SDA) FREE H H L L L H Master-transmitter transmits to slave-receiver. Master reads slave imme