vhdl四位动态e1.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shownum is port(clock,en : in std_logic; dp2,dp1 : in std_logic; ---dp2:百位小数点 dp1:个位小数点 numina,numinb,numinc : in std_logic_vector(3 downto 0); display : out std_logic_vector(6 downto 0); enout : out std_logic_vector(2 downto 0); 控制使能段 dpout : out std_logic); --小数点输出 end; architecture decoder of shownum is signal counter : integer range 0 to 2; signal counter1 : integer range 0 to 1; signal num1 : std_logic; begin a: process(clock,en) variable num : std_logic_v