基于FPGA的静止电压稳定优化器设计.pdfVIP

计算机测量与控制.2015.23(4) 屏法、设计与应用| Computer Measurement Control • ì339 • 文章编号:1671-4598(2015)04 -1339 -04 申图分类号:TP303. 3 文献标识码:人 基于 FPGA 的静止电压稳定优化器设计 黄勇l ，陈慈线，韩呻l ，李克~2 ，罗魏2 (1.三峡大学计算机与信息学院.湖北宜昌 443002; 2. 三峡大学电气与新能源学院.湖北宜昌 443002) 摘要:基于 FPG八设计的 Buck- Boosl 型静止电压稳定优化器.直接串联于市电与敏感负荷之间.当供电电压发生电压骤升或骤降 时，可快速稳定电压.确保敏感负荷不受影响，采用前端整流装置代替固定储能装置可获取更长的故障穿越时间.采用单同步旋转坐 标系软件锁相环 (SSRF-SPLI.l 技术实现电网电压同步.而采用电压双闭环控制技术改善了系统的响应速度.试验结果表明.该装置 能快速稳定电压骤升骤降，并能较好地抑制谐波。 关键词:大规模可编程阵列二升降压:静止电压稳定优化器z 电能质量 Design of Static Voltage Stabilizer Optimizer ßased on FPGA l l l 2 2 H uang Yong • Chen Cifa , Han Shuai , Li Kecheng , Luo Kai ( 1. College of Computer . Information. CTGU. Yichang 443002. China; 2. College of Electrical Engincering . \!ew Energy , CTGU. Yichang 443002. China) Abstract: Thc design 01 Buck - Boosl type static voltage stability optimizer based on F I(;A. directly connected in series between the mains supply and the sensiti\e load扣凹hen the supply voltage occur.s sags or swelb ，口 lastly stablc the voltagεto en叫时 that thc !cnsitive load只 are not affected. Usin日 rectificr circuÎt in hcad in川ead of a fixed energy stürage devicc to get a longcr lault ride-- through time. the usc of base on single synchronous rotating coordinate system software PLL technology to synchronize the voltage of mains. dual closed 一 loop control system is adopted 10 improve the speed of response. The experimental results show that the dcvicc can quickly 川abilize voltage surges and sags. and then can suppress thc harmonics effec