(数字电子技术）CH25门电路的VHDL语言描述及仿真.pdf

2. 5 门电路的VHDL 描述及其仿真 [ 例2 .5 .1 ] 2 输入与非门的VHDL 描述及仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2 IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END nand2; ARCHITECTURE one OF nand2 IS BEGIN y= a nand b; END one; [例2 .5 .2 ] 2 输入或门的VHDL 描述及仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 IS PORT(a, b : IN STD_LOGIC; y: OUT STD_LOGIC); END or2; ARCHITECTURE one OF or2 IS BEGIN y