Static_Timing_Analysis(详尽实用的教程).ppt

Digital ICs Training Digital ICs Training Concepts Covered STA – What is Static Timing Analysis? STA – What is Static Timing Analysis? STA – What is Static Timing Analysis? Limitations of STA What is Dynamic Timing Analysis ? Comparing STA and DTA STA in ASIC Design Flow – Pre layout STA in ASIC Design Flow – Post Layout STA - Timing Graph Introduction STA - Node Types STA - Events At each node is a group of events modeling signal transitions STA - Meeting Timing Q. Am I meeting timing at this node? STA - Meeting Timing Q. Am I meeting late mode timing at this node? STA - Levels STA - Calculating AT STA - Calculating RT STA - Calculating Slack What Does Register Bound Mean ? STA Introduction Summary Concepts Covered Defining Clocks Gated Clock Describing Clock Variations Network, Source, and IO Latency Network Latency Network Latency Clock Skew Clock Skew Clock Skew Clock Skew Jitter Summary: Clocks Basic Terminologies Basic Terminologies Maximum Clock Frequency The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip-flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. Relevant timing parameters Gates: Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL Flip-Flops: Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL Setup time: tsu Hold time: th Basic Terminologies Basic Terminologies Basic Terminologies False paths Paths that physically exist in a design but are not logic/functional paths These paths never get sensitized under any input conditions Multicycle Path Now Switch On To Sequential Timing Circuits Anatomy Of A Pipeline Stage Anatomy Of A Synchronous System Slack Analysis – Data Path types Primary input-to-register paths Delays off-chip + Combinational logic delays up to the first sequential device. Register-to-primary output paths Start at a sequential device CLK-to-Q transition delay + the