单片机IO口（国外英文资料）.docVIP

单片机IO口 First, the structure and working principle of P0 port P0 port 8 bit diagram of a structure, see the following figure: Seen from the figure, P0 port by the latch, and the input buffer switch, a NAND gate, a gate drive circuit and fet. Then, to the right of the picture, labeled P0.X, that is to say, the P0.X pin can be any one of P0.0 to P0.7, i.e., there are 8 circuits in the P0 port that are the same as the figure above. Now lets introduce each of the units that make up the P0 port: Look at the input buffer: P0 in the mouth, there are three state buffer two, in digital circuits, we already knew that three state gate has three states, namely in the output can be high level and low level, and there is a high impedance state (or state) everybody, see chart, the top one is read buffer latch, that is to say, to read the D latch output terminal of the Q data, it is the three state of the buffer read latch control terminal (the label read latch end) effective. The following is a buffer read pin, to read the data on the P0.X pin, the control end of the three state buffers will make the label read pin data transmission will be effective on the pins to the internal data bus on us. The D latch: a latch, usually with a sequential circuit, we know that the timing unit circuit in digital circuits, a trigger can save a number of binary (i.e. maintain function), are used to form a D trigger latch at 32 I/O 51 microcontroller port lines. We all like the D latch in the figure, the D side is the data input, and the CP is the control end (that is, the timing control signal input), Q is the output, and the Q is not the reverse output. For a D trigger, when the D input end of an input signal, if no signal control terminal CP (that is, when no timing pulse arrival) input D data cannot be transmitted to the output terminal of Q and Q non inverting output. If the timing pulse of the timing control terminal CP arrives, then the data input to the D terminal is transmitted to the Q and