数字系统设计【夏宇闻】CPU代码,书中代码有几处的错误概要1.docx

//adder counter用于存放当前结果，当累加器ena接口接受到cpu的load_acc信号时，保存数据总线数据module accum(input clk,input rst,input [7:0]data,input ena,output reg [7:0]accum);always @(posedge clk)beginif(rst)beginaccum = 8b0000_0000;endelse beginaccum = data;endendendmodule//地址译码器module addr_decode(input [12:0]addr,output reg rom_sel,output reg ram_sel);always @(addr)begincasex(addr)13b1_1xxx_xxxx_xxxx : {rom_sel,ram_sel} = 2b01;13b0_xxxx_xxxx_xxxx : {rom_sel,ram_sel} = 2b10;13b1_0xxx_xxxx_xxxx : {rom_sel,ram_sel} = 2b10;default {rom_sel,ram_sel} = 2b00;endcaseendendmodule//地址多路器module adr(input [12:0]pc_addr,input [12:0]ir_addr,input fetch,output [12:0]addr);assign addr = (fetch) ? pc_addr : ir_addr;endmodule//算术运算器module alu(input clk,input rst,input [7:0]data,input [7:0]accum,input [2:0]opcode,input alu_ena,output reg zero,output reg[7:0]alu_out);parameter HLT = 3b000, SKZ = 3b001, ADD = 3b010, ANDD = 3b011, XORR = 3b100, LDA = 3b101, STO = 3b110, JMP = 3b111;//此处有疑问，省略了assign zero = !accum;always @(posedge clk)beginif(alu_ena)begincase (opcode)HLT : alu_out = accum;SKZ : alu_out = accum;ADD : alu_out = data + accum;ANDD: alu_out = data accum;XORR: alu_out = data ^ accum;LDA : alu_out = data;STO : alu_out = accum;JMP : alu_out = accum;default : alu_out = 8bxxxx_xxxx;endcaseendendendmodule//时钟产生器module clk_gen(input clk,input reset,output reg fetch,output reg alu_ena);reg [7:0]state;parameter S1 = 8b0000_0001, S2 = 8b0000_0010, S3 = 8b0000_0100, S4 = 8b0000_1000, S5 = 8b0001_0000, S6 = 8b0010_0000, S7 = 8b0100_0000, S8 = 8b1000_0000, idle = 8b0000_0001;always @(posedge clk)beginif(reset)beginfetch = 0;alu_ena = 0;state = idle;endelse begincase (state)S1:beginalu_ena = 1;state = S2;endS2:beginalu_ena = 1;state = S3;endS3:beginfetch = 1;state = S4;endS4:beginstate = S5;endS5:state = S6;S6:state = S7;S7:beginfetch = 0;state = S8;endS8:state = S1;//idle: state = S1;default state = idle;endcaseendendendmodule//程序计数器module counter(input clk,input rst,input load,output reg [12:0]pc_addr,input [1