电子科技大学《数字逻辑设计及应用》Lec18-chap 7.pptVIP

* 5. Draw state diagram 6. Draw timing diagram (optional ) 0010 0100 1000 Y0Y1Y2Y3 0001 由时序图可看到，该电路是能循环输出4个脉冲的顺序脉冲发生器(脉冲分配器) 7.3.4 state machine analysis Control（控制型时序电路） Sequential detection（序列检测/产生型） counting（计数型时序电路） * Back ups * Prepared by Jin Digital Logic Design and Application * Digital Logic Design and ApplicationLecture #18 Clocked Synchronous State-Machine Analysis UESTC, Spring 2013 7.3.1 state machine structure * Finite state（有限状态）：实际时序电路的状态个数是可列的有限个，因此时序电路又被称为有限状态机（Finite state machine）。 （log2n） 7.3.1 state machine structure * 2 D F.F can store four states. 7.3.1 state machine structure * 时钟信号 触发类型取决于内部的FF类型； Edge trigger，pulse trigger 时序电路的输出变化与CLK的关系取决于状态机的类型。 Mealy，Moore，Pipelined output * 7.3.1 state machine structure State-machine structure Mealy machine model Mealy machine的名字来自这个概念的提出者，在1951年写了A Method for Synthesizing Sequential Circuits的状态机的先驱 G. H. Mealy Output=G(current state, inputs) Next state=F(current state, inputs) Next-State logic F State Memory Output logic G 7.3.1 Finite state machine structure * Next State Logic F State Memory clock Output Logic G State-machine structure Moore machine model Moore状态机是输出只由当前状态直接确定的有限状态机。 Output= G (current state) * EN EN’ Q0 Q0’ Q1 Q1’ EN MAX Q0 Q1 CLK D0 D1 Mealy machine Moore machine MAXS Example state machine A Mealy machine has equivalent Moore machine model. 7.3.4 state machine analysis * Current Output=G( ) Q（Qk, …Q1） Q*（Q*k, …Q*1） Next Output = G (Q*, I*) I（Ik, …I1） I*（Ik, …I1） Q*=T ( ) T 输出逻辑 output equation Excitation/input= 下一状态逻辑 转移方程 transition equation F (Q, I) prediction current state, inputs * Clocked Synchronous State Machine Analysis Derive excitation equation from circuit diagram F (Q, I) Derive output equation from the circuit diagram Y=G (Q, I) Determine transition equation Q*=T (F (Q, I)) 7.3.4 state machine analysis Combinational Combinational Sequential Cons