电子科技大学《数字逻辑设计及应用》Lec20-chap 8.pptVIP

CLK EN clear and load Q0 Q1 Q2 Q3 D0 D1 D2 D3 (Qi-1 · … · Q0) ?Qi counting * synchronous clear input LD_L CLR_L CLK QA A counting function Qi* = (Qi-1 · … · Q1 · Q0) ? Q 0 0 0 0 0 0 * synchronous load input LD_L CLR_L CLK QA A counting function Qi* = (Qi-1 · … · Q1 · Q0) ? Q 0 1 1 0 2-to-1 MUX * ENP and ENT enable inputs ENP ENT EN RCO clear “ripple carry out” signal ripple carry out RCO=ENT · QD · QC · QB · QA * operate in a free-running mode Free-running ?16 Count if ENP andENT both asserted. Load if LD is asserted(overrides counting). Clear if CLR is asserted(overrides loading and counting). All operations take place on rising CLK edge. RCO is asserted if ENT is asserted and count = 15. * A free-running 4-bit ’163 counter can be used as ?2, ?4, ?8 and ?16 frequency divider. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 waveforms for a free-running 4-bit ’163 counter * 4. Other MSI Counters 74x160、74x162 Modulo-10 counter or decade counter ( BCD ) 0 1 2 3 4 5 6 7 8 9 0 QA QB QC QD QC and QD ?10, duty cycle ≠ 50％ * 4. Other MSI Counters 74x169 up/down counter 74x160、74x162 Modulo-10 counter or decade counter ( BCD ) UP/DN When UP/DN is 1, it counts in ascending. When UP/DN is 0, it counts in descending. enable inputs carry out active-low Jin. UESTC Digital Logic Design and Application * Digital Logic Design and ApplicationLecture #20 Chapter 8Sequential Logic Design Practices UESTC, Spring 2013 * Chapter 7 Sequential Logic Design Principles Combinational logic circuit Outputs = f ( current inputs ) Sequential logic circuit Outputs = f ( current inputs + entire input history ) stored in memory elements Latches and Flip-Flops feedback sequential circuit clocked synchronous state machine Mealy machine Moore machine 虽然组合逻辑电路能够很好地处理像加、减等这样的操作，但是要单独使用组合逻辑电路，使操作按照一定的顺序执行，需要串联起许多组合逻辑电路，而要通过硬件实现这种电路代价是很大的，并且灵活性也很差。为了实现一种有效而且灵活的操作序列，需要构造一种能够存储各种操作之间的信息的电路→时序电路。 时序电路可以提高器件利用效率。 * Chapter 7 Sequential Logic Design Principles Clock signal clock period, c