EDA程序设计参考 数字时钟的原理图VHDL混合设计(前六个LED)（EDA programming reference digital clock principle diagram VHDL hybrid design (the first six LED)）.docVIP

EDA程序设计参考 数字时钟的原理图VHDL混合设计(前六个LED)（EDA programming reference digital clock principle diagram VHDL hybrid design (the first six LED)） seccount.vhd - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * library ieee; use ieee.std _ logic _ 1164.all; use ieee.std _ logic _ unsigned.all; - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * seccount entity. port (en, rtd _: std logic; co: _ out std logic; a, b: out std logic vector _ _ (3 downto 0)); end seccount; - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * architecture rtl of seccount is signal aout, bout: std logic vector _ _ (3 downto 0); signal cout _: std logic; begin process (en, clk, rtd) begin if (r = 0) then aout = 0000. bout = 0000. cout = 0; elsif (clkevent and clk = 1) then if (en = 1) then if (aout = 9) then aout = 0000. if (bout = 5) then bout = 0000. cout = 1; else bout = bout + 1; end if; else aout = aout + 1; cout = 0; end if; end if; end if; end process; = aout; b = bout. the = cout; end rtl. mincount.vhd - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * library ieee; use ieee.std _ logic _ 1164.all use ieee.std _ logic _ unsigned.all - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * mincount entity. port ( en1, en2, clk: in std _, rtd logic; co: _ out std logic; a, b: out std logic vector _ _ (3 downto 0)); end mincount; - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * architecture rtl of mincount is signal aout, bout: std logic vector _ _ (3 downto 0); signal cout _: std logic; begin