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A high-speed sample-and-hold technique using (高速取样保持的技术使用)
IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 26, NO. 4, APRIL 1991 643
A High-speed Sample-and-Hold Technique
Using a Miller Hold Capacitance
Peter J. Lim, Student Member, IEEE, and Bruce A. Wooley, Fellow. IEEE
Abstract -This paper introduces a circuit technique for increasing the circuit without the need for precise capacitors or an increase
precision of an open-loop sample-and-hold circuit without significantly in capacitor size, which would result in a corresponding
reducing the sampling speed. With this technique, the sampling error
resulting from input-dependent charge injection of the sampling switch decrease in sampling rate. In this proposed approach the
is attenuated by sampling the input voltage onto a capacitance that is input is sampled onto an equivalent hold capacitance that is
small during the sample mode but is, in effect, increased during the small during the sampling mode but is increased during the
transition to the hold mode through the action of Miller feedback. The hold mode by means of Miller feedback. A sample-and-hold
technique thus allows for a high sampling speed without the precision
circuit based on the approach has been designed and fabri-
penalty traditionally associated with open-loop sample-and-hold cir-
cuits. cated in a 1-pm CMOS technology, and an order-of-magni-
A sample-and-hold circuit based on the proposed approach has been tude reduction in the input-dependent charge injection of
designed and fabricated in a 1-pm CMOS technology, and an order-of-
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