- 1、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
- 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载。
- 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
- 4、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
- 5、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们。
- 6、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
- 7、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
8051单片机输入输出端口的结构(8051 MCU input and output port structure)
Today, we study the microcontrollers input / output port structure.
8051 SCM has four 8 bit parallel I/O port, recorded as P0, P1, P2 and P3., each port is 8 bit quasi two-way port, a total of 32 pins. Each I/O line can be used independently as input or output.
Each port includes a latch, an output driver that can latch data for output and can buffer data for input. In a system without on-chip extended memory, each of these four ports can be used as a quasi bidirectional universal I/O port.
In an on-chip extended memory system, the P2 port sends a 8 bit address and the P0 port is a bidirectional bus, sending 8 bit address and data input / output respectively. 8051 SCM four I/O port circuit design is very clever, familiar with I/O port logic circuit, not only conducive to the correct and reasonable use of ports, but also the design of SCM peripheral logic circuit inspired.
PO port:
Each bit of the P0 port consists of an output latch, two three state input buffers, an output drive circuit, a control circuit, and gate, inverter, and MUX control.
When the CPU makes the control line C=0, the NC switch MUX is down, and the P0 port is the universal I/O port
When C=1, the switch pulls out the output to the inverter, and the port divides into address / data bus usage
Lets first look at the P0 port as a I/O port:
When the 8051 - component system has no out - of - memory memory, the CPU reads and writes to the on-chip memory and the I/O port. Executes the MOV MOVC instruction is executed or under the condition of EA=1, the control line automatically by the hardware C=0, switch MUX backward, its output level T2 and latch Q back end connected; at the same time, because the gate output is 0, on the field effect in the output stage of tube T1 is in off state, therefore, the output stage is open drain circuit. At this point, the P0 port can be used as a general I/O port.
General I/O port and input and output two operations,
您可能关注的文档
- ttt-培训师培训(Ttt- trainer training).doc
- uchome模板全解析(Full resolution of UCHOME templates).doc
- 刚上班,懂规矩么,别因为一个动作毁了自己(Just go to work, understand the rules, do not destroy yourself because of an action).doc
- 公共管理论文--论以人为本与高校图书馆现代化信息化管理(Public management thesis -- on human centered and modern information management of University Library).doc
- 公共关系平时作业(二)(Usual work on public relations (two)).doc
- ug 快捷键(ug 快捷键).doc
- ug6.0命令(Ug6.0 command).doc
- 公共管理论文--浅析中职学校图书馆管理模式的创新(Public management paper -- Analysis of the innovation of library management mode in secondary vocational school).doc
- 公共管理论文--以人为本 构建和谐图书馆(Public management papers -- building a harmonious library with people first).doc
- 公共建筑设计原理笔记(Notes on design principles of public buildings).doc
- 798艺术区(798 Art Zone).doc
- a10-约束本构关系-细网格(A10- constrained constitutive relation - fine mesh).doc
- abbs调查(Abbs survey).doc
- abs塑料电镀前处理工艺(Pretreatment process of ABS plastic electroplating).doc
- acaa网络设计师模拟题(ACAA network designer simulation).doc
- acca免试条件(ACCA exemption condition).doc
- 959-初二物理浮力试题训练(959- two day physics buoyancy test training).doc
- ad6画板(AD6 drawing board).doc
- adc打法及重要注意事项(ADC tactics and important points for attention).doc
- accountant职业(accountant职业).doc
原创力文档


文档评论(0)