FPGACPLD数字时钟的实现(原代码).docVIP

数字时钟的综合设计 一、设计任务 1、具有时、分、秒计时显示功能，最大计时为23：59：59。 2、用CPLD/FPGA设计制作成数字时钟的专用芯片，结合LED数码管构成一个能够实现调时和调分的数字时钟。 二、总体设计框图 三、模块设计具体化 1、设计思想 本设计是基于Altera公司的CycloneⅡ系列EP2C35F672C芯片， 采用层次化设计方式，先设计底层的器件如秒计数器、分计数器、时计数器、2选1选择器、译码器，顶层设计采用原理图形式，将底层各个器件连接起来组合成一个数字时钟专用芯片。 2、VHDL程序代码 a、秒计数器程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity second is port( clk: in std_logic; enmin : out std_logic; daout : out std_logic_vector(6 downto 0)); end second; Architecture behave of second is signal count: std_logic_vector(6 downto 0); begin daout= count; process(clk) begin if (clkevent and clk=1) then if count(3 downto 0)=1001 then if count(6 downto 4)=101 then count=0000000;enmin=1; else count(3 downto 0)=0000; count(6 downto 4)=count(6 downto 4)+1; end if; else count(3 downto 0)=count(3 downto 0)+1;enmin=0; end if ; end if; end process; end behave; b、分计数器程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity minute is port( clk: in std_logic; enhour : out std_logic; daout : out std_logic_vector(6 downto 0)); end minute; Architecture behave of minute is signal count: std_logic_vector(6 downto 0); begin daout= count; process( clk) begin if (clkevent and clk=1) then if count(3 downto 0)=1001 then if count(6 downto 4)=101 then count=0000000;enhour=1; else count(3 downto 0)=0000; count(6 downto 4)=count(6 downto 4)+1; end if; else count(3 downto 0)=count(3 downto 0)+1;enhour=0; end if ; end if; end process; end behave; c、时计数器程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hour is port( clk: in std_logic; daout : out std_logic_vector(5 downto 0)); end hour; Architecture behave of hour is signal count: std_logic_vector(5 downto 0); begin daout= count