第6章 数字集成电路基本单元与版图4----ic layout design----tools from cadence.pptVIP

第6章 数字集成电路基本单元与版图4----ic layout design----tools from cadence.ppt

  1. 1、本文档共36页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
  5. 5、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
  6. 6、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们
  7. 7、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
  8. 8、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
第6章 数字集成电路基本单元与版图4----ic layout design----tools from cadence

Electronic Design Automation Tools from Cadence Agenda Overview of Cadence Setup the environment Main Stream EDA tools in Analog Design Flow Main Stream EDA tools in Digital Design Flow Profile of Cadence Cadence Design Systems, Inc. was established in 1988 through the merger of two EDA pioneers—ECAD, Inc. and SDA Systems. Cadence is the worlds largest provider of electronic design automation (EDA) products and services. Cadence is a global company with 5,700 employees in over 30 major locations, and revenues of nearly $1.3 billion in 2000 Overview of Cadence Cover almost every aspects of electronic design, including ASIC, FPGA,PCB. 综合工具(synthesis tools)不及Synopsys 在schematic design and simulation, layout design 方面有明显优势。 支持SKILL语言 Overview of Cadence Cadence provides complete solutions to both analog and digital IC design flow Virtuoso custom design platform specification-driven environment(规则驱动环境) multi-mode simulation(多模式仿真) accelerated layout(快速布图) Silicon analysis (硅验证) Encounter digital IC design platform minimizes time to wires and full-chip iteration time a unified database with massive capacity of up to 50 million gates Overview of Cadence Virtuoso Design Platform Schematic editing tool Composer Circuit simulation tool Spectre Layout Editing tool Layout editor Layout verification tool Diva Dracula Assura Encounter Digital Design Platform Synthesis tool Encounter RTL compiler Produces a global logic structure made for timing closure Physical synthesis tool First encounter GPS(Global Physical Synthesis) supports both RTL-to-placed gates and netlist-to-placed gates design styles produce a silicon virtual prototype of the physical design(硅虚拟原型) Place and route tool Nano encounter Overview of Cadence We would focus on: Circuit Design tool: Composer Layout design tool: Virtuoso Layout Editor Layout verification tools: Dracula and Diva Setup the environment Supporting Files: .cshrc .cdsenv .cdsinit cds.lib Technology file (.tf) Display file(.drf) Setup the enviro

您可能关注的文档

文档评论(0)

sandaolingcrh + 关注
实名认证
文档贡献者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档