Static_Timing_Analysis(详尽实用教程).ppt

款夕账劣真歧乾快角滥插寄当蔬锄澎茁安甥袍布悉荫吉箱眷着妮那早翔窿Static_Timing_Analysis(详尽实用教程)Static_Timing_Analysis(详尽实用教程);Concepts Covered;STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design. ;STA – What is Static Timing Analysis?;STA – What is Static Timing Analysis?;Limitations of STA;What is Dynamic Timing Analysis ?;Comparing STA and DTA;STA in ASIC Design Flow – Pre layout;STA in ASIC Design Flow – Post Layout;The Timing Graph;STA - Timing Graph Introduction;STA - Node Types;STA - Events;STA - Meeting Timing;STA - Meeting Timing;STA - Levels;1.0;1.0;1.0;What Does Register Bound Mean ?;STA Introduction Summary;Understanding and Describing Clocks;Concepts Covered;Defining Clocks;Gated Clock;Describing Clock Variations;Network, Source, and IO Latency;Network Latency;Network Latency;Clock Skew ;Clock Skew;Clock Skew;Clock Skew;Jitter;Summary: Clocks;Sequential Timing Circuits;Basic Terminologies;Basic Terminologies;Maximum Clock Frequency;Basic Terminologies;Basic Terminologies;Basic Terminologies;Multicycle Path;D;Now Switch On To Sequential Timing Circuits;Anatomy Of A Pipeline Stage;Anatomy Of A Synchronous System;Three Steps in Static Timing Analysis;What is a Timing Path?;Organizing Timing Paths Into Groups;Slack Analysis – Data Path types;Primary input-to-register paths Delays off-chip + Combinational logic delays up to the first sequential device. Register-to-primary output paths Start at a sequential device CLK-to-Q transition delay + the combinational logic delay + external delay requirements Register-to-register paths Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times. Primary input-to-primary output paths Delays off-chip + combinational logic delays + external delay requirements. ;Hold Slack calculation;Setup Slack calculation;Calculate the setup slack;A Timing Example:;Absolute Clock Skew – A Definition;Relative Clock Skew;Fa