16位乘法器学习笔记Verilog语言源程序+仿真程序.docVIP

LCD1602显示源程序如下： module lcd1602(input clk, //60M input rst_n, output lcd_p, //Backlight Source + lcd屏幕背光 output lcd_n, //Backlight Source - output reg lcd_rs, //0:write order; 1:write data output lcd_rw, //0:write data; 1:read data output reg lcd_en, //negedge 在lcd_en下降沿需保证数据有效 output reg [7:0] lcd_data); mux16 mul(.rst_n(rst_n),.clk(clk),.start(start),.ain(data0),.bin(data1),.yout(data2),.done(done