design optimization of transistors used for neural recording优化设计的晶体管用于神经记录.pdfVIP

Hindawi Publishing Corporation Active and Passive Electronic Components Volume 2012, Article ID 472306, 10 pages doi:10.1155/2012/472306 Research Article Design Optimization of Transistors Used for Neural Recording Eric Basham and David Parent Electrical Engineering Department, San Jose State University, San Jose, CA 95192-0084, USA Correspondence should be addressed to David Parent, david.parent@ Received 16 July 2011; Revised 5 October 2011; Accepted 18 October 2011 Academic Editor: Mingxiang Wang Copyright © 2012 E. Basham and D. Parent. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on the g m/Id design approach to optimize a single-stage common-source amplifier design. The g m/Id design approach facilitates in circuit characterization of the neuron- FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current