中断机制（Interrupt mechanism）.docVIP

中断机制（Interrupt mechanism） If you are using the SD card or NandFlash, will be used to ROMCode, the interrupt vector in 0x14000, followed by Reset Undef SWI Prefetch Abort Data Abort reserved IRQ FIQ. For example: IRQ interrupt occurs when the program will automatically jump to the 0x14018. The following IRQ example: (1) when the IRQ interrupt, the program counter PC to jump to 0x14018; (2) ROMCode and immediately let PC jump to start from 0x0x4020FFC8 RAM interrupt vector, Reset interrupt the direct implementation of the ROMCode does not require the RAM interrupt vector, so the RAM interrupt vector from Undef, IRQ to 0x4020FFDC (3) in all of the above RAM are stored in the interrupt vector a PC=[RAM interrupt vector address +0x1C] instruction (note in brackets is the address of the content), this is done by the ROMCode normal startup, but I write code again or get on the side, in IRQ, RAM interrupt vector +0x1C=0x4020FFDC+0x1C=0x4020FFF8 address (4) so you only need to deposit the IRQ function in the 0x4020FFF8 address can be, in my OclO, a piece of code in cpu/omap-3/start.S: AwSRAMVectorBase: .word SRAM_VECTORS_BASE SRAM_VECTORS_BASE in include/asm/arch-omap3/omap35xx.h is defined as #define SRAM_VECTORS_BASE 0x4020FFC8 by Rom / / Code specified interrupt table address LDR R1, awSRAMVectorBase build vect addr / * * / Next: Ldmia R0, {r3-r9} copy from! Source address [r0] * / / * Stmia R1, {r3-r9} copy to! Target address [r1] * / / * CMP R0, R2 until source end address [r2] * / / * Bne Next loop until equal / * * / This cycle is all the interrupt response function in response to the first address address, when executing PC=[RAM interrupt vector address +0x1C], can response to jump function. Each function is composed of two parts: the +C assembly, assembly in start.S IRQ IRQVectorA: Stmfd SP, {r0 R12, lr}! BL IRQVectorC Ldmfd SP, {r0 R12, lr}! Subs PC, LR, #4 / / when the destination register for the PC, s said CPSR is returned from the SPSR at the same time Where IR