如何读懂时序图.pdf

/itangcle CPE/EE 421 Microcomputers WEEK #10 Interpreting the Timing Diagram 如何读懂时序图 The 68000 Read Cycle 2 Timing Diagram of a Simple Flip-Flop Idealized form of the timing diagram Actual behavior of a D flip-flop Data hold time Data setup time Max time for output to become valid after clock Alan Clements 3 General form of the timing diagram An alternative form of the timing diagram 4 Alan Clements The Clock • A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations 一个微处理器需要时钟,提供一系列的计时脉冲来控制 它的内部操作 • A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7 一个6800 芯片的储存器最小能过接收8 个从S0 到S7 的时钟脉冲. A memory access begins in clock state S0 and ends in state S7 6 Alan Clements The most important parameter of the clock is the duration of a cycle, tCYC. Alan Clements 7 Alan Clements 8 Address Timing 地址时序 • We are interested in when the 680