网站大量收购独家精品文档,联系QQ:2885784924

数字设计基础双语教学版课件作者英BarryWilknson双语课件(第4章节).ppt

数字设计基础双语教学版课件作者英BarryWilknson双语课件(第4章节).ppt

  1. 1、本文档共30页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
尚辅网 / 4. Flip-flops and counters 4.1 Sequential circuits 4.2 Memory design using gates 4.3 Flip-flops 4.4 Registers 4.5 Counters 4.1 Sequential circuits 1. Concept of sequential circuit The logic circuits whose outputs depend not only on the present logic input values but also on previous logic input and output values are called sequential circuits. Counter is a common example of sequential circuit. 4.1 Sequential circuits (2)Asynchronous sequential circuit A sequential logic circuit that does not use a synchronizing clock signal is called asynchronous sequential circuit. 2. Classification of sequential circuit (1)Synchronous sequential circuit A sequential logic circuit whose output changes are initiated by an input clock signal and in which the outputs change upon the required clock signal transition is called a synchronous sequential circuit. 4.2 Memory design using gates A logic circuit can maintain a constant output value by the use of feedback whereby the output is connected to the inputs to reinforce the output value. Set-reset memory design ⅰ) R = 0, S = 1, Q = 0; ⅱ) R = 1, S = 0, Q = 1; From the circuit, we can get: Once the output has been forced to a 0 or a 1, the input can return to a 1 and the output will remain unchanged. 4.2 Memory design using gates It is often convenient to have both a true output Q and a complementary output Q which in normal operation of the memory circuit has the opposite logical value to Q. The memory design shown below is called a latch. The latch can store one binary value, but its outputs will change when one of the inputs changes to a 0. Disadvantage of latch: 4.2 Memory design using gates Sometimes we have active high inputs memory design. 4.3 Flip-flops Normally we want the output changes to be synchronized with a clock signal. Such memory designs are called flip-flops. A flip-flop can store a single bit by producing an output of a 0 or a 1 continuously until changed b

您可能关注的文档

文档评论(0)

带头大哥 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档