ASIC和FPGA的混合系统.doc

  1. 1、本文档共14页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
ASIC和FPGA的混合系统

英文资料及中文翻译 A hybrid ASIC and FPGA Architecture FPGA is English Field Programmable Gate Array abbreviation, namely the scene programmable gate array, it is the product which in PAL, GAL, EPLD and so on in the programmable component foundation further develops. It is took in the special-purpose integrated circuit (ASIC) domain one kind partly has custom-made, both solves has had custom-made the electric circuit which the electric circuit appears the insufficiency, and has overcome the original programmable component gate number limited shortcoming. FPGA used logical unit array LCA (Logic Cell Array) this kind of new concept, the interior including has been possible to dispose logical module CLB (Configurable Logic Block), output load module IOB (Input Output Block) and internal segment (Interconnect) three parts. The FPGA essential feature mainly has: Uses FPGA to design the ASIC electric circuit, the user does not need to throw the piece production, can obtain the chip which comes in handy. - - 2) FPGA may make other all to have custom-made or partly to have custom-made the ASIC electric circuit the experimental preview. The FPGA interior has the rich trigger and the I/O pin. FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components. FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components. FPGA uses the high speed CHMOS craft, the power loss is low, may and CMOS, the TTL level is compatible.   It can be said that, the FPGA chip is the small batch system enhances the system integration rate, one of reliable best choices. FPGA is by deposits the procedure establishes its active status in internal RAM, therefore, time work needs to carry on the programming to internal RAM .The user may act according to the different disposition pattern, selects the different programming method.  When adds the electricity, the FPGA

文档评论(0)

153****9595 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档