6.CortexA9微处理器单元子系统.PDF

6. Cortex-A9微处理器单元子系统 November 2012 cv_54006-1.2 cv_54006-1.2 ® ® Altera SoC FPGA 器件中的硬核处理器系统 (HPS) 包括一个独立的、全功能的 ARM Cortex ™- A9 MPCore ™单或双核 32 位应用处理器。Cortex- A9 MPU 子系统包括一个 Cortex- A9 MPCore、一个第 2 层 (L2) 缓存、一个加速器一致性端口 (ACP)ID 映射器和 调试模块。 Cortex- A9 MPU 子系统的功能 Altera Cortex- A9 MPU 子系统提供以下功能: ■ 一个或两个 Cortex- A9 处理器 ■ 中断控制器 ■ 每个处理器的专用间隔和看门狗计时器 ■ 全局计时器 ® ® ■ TrustZone 系统安全扩展 (TrustZone system security extensions) ■ 对称多处理 (SMP) 和非对称多处理 (AMP)模式 ■ 调试模块 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest