可编程器件cpld-7.pptVIP

第7章 基本逻辑电路设计7.1 组合逻辑电路设计 * 门电路 * 编码器、译码器 、 多路选择器 *加法器、求补器 *三态门、总线缓冲器 7.1.1 门电路 二输入异或门 二输入异或门的逻辑表达式如下所示： 例:采用行为描述方式设计的异或门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2_v1 IS PORT(a,b: IN STD_LOGIC; y: OUT STD_LOGIC); END xor2_v1; ARCHITECTURE behave OF xor2_v1 IS BEGIN y = a XOR b; END behave; 例：采用数据流描述方式设计的异或门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2_v2 IS PORT(a,b: IN STD_LOGIC; y: OUT STD_LOGIC); END xor2_v2; ARCHITECTURE dataflow OF xor2_v2 IS BEGIN PROCESS (a,b) VARIABLE sel : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel := a b; CASE sel IS WHEN 00= y =0; WHEN 01= y =1; WHEN 10= y =1; WHEN 11= y =0; WHEN OTHERS = y =X; END CASE; END PROCESS; END dataflow; 7.1.2 编码器 用一组二进制代码按一定规则表示给定字母、数字、符号等信息的方法称为编码，能够实现这种编码功能的逻辑电路称为编码器。 例：采用行为描述方式的8线—3线编码器VHDL源代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder83_v1 IS PORT(I0,I1,I2,I3,I4,I5,I6,I7: IN STD_LOGIC; A0,A1,A2: OUT STD_LOGIC); END coder83_v1; ARCHITECTURE behave OF coder83_v1 IS BEGIN A2 = I4 OR I5 OR I6 OR I7; A1 = I2 OR I3 OR I6 OR I7; A0 = I1 OR I3 OR I5 OR I7; END behave; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder83_v2 IS PORT( I: IN STD_LOGIC_VECTOR(7 DOWNTO 0); A: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END coder83_v2; ARCHITECTURE dataflow OF coder83_v2 IS BEGIN PROCESS (I) BEGIN CASE I IS WHEN A =111; WHEN A =110; WHEN A =101; WHEN A =100; WHEN A =011; WHEN A =010; WHEN A =001; WHEN OTHERS = A =000; END CASE; END PROCESS; END dataflow; 译码器