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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 3, JUNE 1987 335
A CMOS Chopper Amplifier
CHRISTIAN C. ENZ, STUDENT MEMBER, IEEE, ERIC A. VITTOZ, MEMBER, IEEE, AND
FRAN~OIS KRUMMENACHER
Abstracf —This paper describes a highly sensitive CMOS chopper Section II will review different low-frequency noise and
amplifier for low-frequency applications. It is realized with a second-order offset reduction techniques, emphasizing the fundamental
low-pass selective amplifier using a continuous-time filtering technique.
differences between the autozero and chopper techniques.
The circuit has been integrated in a 3- pm p-well CMOS technology. The
chopper amplifier dc gain is 38 dB with a 2@-Efz bandwidth. The equiv- Section III will present the realization of the selective
alent inpnt noise is 63 nV/dHz and free from l/~ noise. The input offset amplifier, whereas the theoretical performances of the
is below 5 VV for a toning error less than 1 percent. The amplifier chopper amplifier will be discussed in Section IV. Finally
consumes only 34 ~W. the circuit implementation and the experimental results
will be presented in Sections V and VI.
1. INTRODUCTION
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