DC脚本及解释.docVIP

#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you... #script for Design Compiler# Language? : TCL# Usage???? :#?????????? 1) make sure the lib in the current directory#?????????? 2) if you have the file .synopsys_dc.setup,#????????????? set synopsys_dc_setup_file 1,#????????????? if not, set synopsys_dc_setup_file 0#?????????? 3) change Step 3 : Variables to what you want#????????????? Especially : top module name, clock name,#????????????? reset name, all files name, and period#?????????? 4) typing dc_shell-t -f run_72.tcl | tee -i run.log#?#======================================================== set synopsys_dc_setup_file 0#-----------------------------------------------------# Step 1 :# Setting Up path and library：# If you have edited the file .synopsys_dc.setup, then you can skip over this step#-----------------------------------------------------if { $synopsys_dc_setup_file == 0} {set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]set target_library? {typical.db}#set target_library? {CSM35OS142_typ.db};# if you want use typical library,change to typical.db#set link_library? [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db]set link_library? [list {*} $target_library]}#set symbol_library? {csm18ic.sdb csm18io.sdb}#set synthetic_library? {dw_foundation.sldb};# Design Wareset command_log_file?? command.log #-----------------------------------------------------# Step 2 :# Compile Swithes#-----------------------------------------------------#set verilogout_no_tri????????????????? true ;# if inout used, tri net will be used#通过将三态（tri）逻辑声明成线网（wire）来确保网表中不会出现三态逻辑，因为一些布线工具很难读取包含tri、tran源语、assign语句的网表，对于“inout”类型的port,DC产生tri wire 语句和tran 源语，对于tri，还会产生assign语句set test_default_scan_style????????? multiplexed_flip_flop#设置扫描链的类型，还可以通过set_scan_configuration -style来设置set link_force_case????????????????? c