一种基于累积分布函数的抖动测量方法-北京大学学报自然科学版.PDFVIP

北京大学学报 ( 自然科学版), 第 48 卷 , 第 3 期 , 2012 年 5 月 Acta Scientiarum Naturalium Universitatis Pekinensis, Vol. 48, No. 3 (May 2012) 一种基于累积分布函数的抖动测量方法 1,2 1,2,† 1 郭健 冯建华 叶红飞 1. 北京大学微电子学系 , 北京 100871; 2. 北京大学深圳研究生院集成微系统科学工程与应用重点实验室 , 深圳 518055; † 通信作者 , E-mail: fengjh@ 摘要 提出一种基于累积分布函数(CDF) 的抖动测量方法, 以解决在测试高频时钟信号抖动中遇到的延迟器 件不匹配、占用芯片面积过大和受高频振荡信号限制等问题。采用 65 nm CMOS 工艺完成了测试电路的设计 和功能模拟, 模拟结果表明该电路可用于测量 2.5 GHz 时钟抖动值, 抖动测量精度达到 1 ps。 关键词 时钟抖动; 内建抖动测试; 时间数字转换器 中图分类号 TN407 A New On-Chip Jitter Measurement Method Based on Cumulative Distribution Function GUO Jian1,2, FENG Jianhua1,2,†, YE Hongfei1 1. Department of Microelectronics, Peking University, Beijing 100871; 2. Key Laboratory of Integrated Microsystem Science Engineering and Applications, Shenzhen Graduate School of Peking University, Shenzhen 518055; † Corresponding author, E-mail: fengjh@ Abstract The authors present a new on-chip jitter measurement method based on cumulative distribution function (CDF) to solve the problem of the mismatch of the delay line, taking up too much chip area and limited by high frequency oscillator signal, which are encountered in measuring multi-GHz clock jitter. The complete circuit is designed and implemented based on the 65 nm CMOS process. The simulation results show that the circuit is able to operate at 2.5 GHz and achieves a timing resolution up to 1 ps. Key words timing jitter; built-in jitter measurement (BIJM); time-to-digital (TDC) 随着集成电路特征尺寸不断减小, 工作频率越 当被测信号的频率超过 5 GHz 时, 测试价格变得非 来越高。当数据和时钟速