接收訊框描述傳送訊框描述訊框資料緩衝區.ppt

Samsung ARM S3C4510B Product overview System manager Unified instruction/data cache I2C bus controller Ethernet controller DMA controller UART 32-bit timers I/O Ports Interrupt Controller I2C Serial Bus 特點 僅用2條線就能在IC間傳送資料 不需使用位址解碼IC 硬體特性 數位IC的I/O一般可分為Totem-pole, Open collector, 和Tri-state I2C介面本身為Open Drain 需外加提升電阻 I2C包括兩條線 SCL (Serial clock) SDA (Serial Data) 在I2C Bus上的元件皆有其唯一位址 I2C Termination The Data Transfer of I2C I2C-bus is a multi-master bus Case 1: A master IC wants to send data to another IC (slave): 1. Master addresses slave 2. Master sends data to the slave (master is transmitter, slave is receiver) 3. Master terminates the data transfer Case 2: A master IC wants to receive information from another IC (slave): 1. Master addresses slave 2. Master receives data from the slave (master is receiver, slave is transmitter) 3. Master terminates the data transfer Muster IC must generate the timing signals and terminate the data transfer Example of I2C connection I2C匯流排協定 開始: master須送出”開始”信號才能取得I2C bus控制權 SCL和SDA保持在高電位 Master先在SDA送出低電位, 經一小段時間後,再將SCL變成低電位 結束： SCL保持在高電位，SDA由低電位到高電位 位址: 每一個送到Bus上的資料都必需是8-bit 位址僅有7-bit, 最後再外加一R/W Bit A completed data transfer S3C4510B I2C bus block diagram Ethernet Controller 乙太網路控制器的資料結構 接收訊框描述 傳送訊框描述 訊框資料緩衝區 傳送訊框資料緩衝區的資料結構 接收訊框資料緩衝區的資料結構 DMA Controller Two general DMA (GDMA) controller Memory-to/from-memory UART-to/from-memory Can be started by software and/or by an external DMA request (nXDREQ) GDMA special registers Data Transfer Mode – Single mode Data Transfer Mode – Block mode Data Transfer Mode – Demand mode 32-bit Timer Provide two 32-bit timer The timer can operate in Interval mode fTOUT = fMCLK/Timer data value Toggle mode fTOUT = fMCLK/2*Timer data value Timer operation guidelines When a timer is enabled Load the data register value to its count register and begin decrement the count register value When the timer interval expires, the associated interrupt is generated. The timer data register value is rel