数据库 ch6_3m.pptVIP

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Agenda Other Features in VHDL Generate Assert Function Overloading FILE IO Generate Example (1) ram32 : ram_0 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(7 downto 0)); ram_1 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(15 downto 8)); ram_2 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(23 downto 16)); ram_3 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(31 downto 24)); end generate ram32; Generate Example (2) ram32 : for i in 3 downto 0 generate ram :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(8*i+7 downto 8*i)); end generate ram32; Generate Label: for ParameterName in Range generate ConcurrentStatements... end generate [Label]; Generate Example (3) Generate Example (4) adder : for i in 0 to wid-1 generate ls_bit : if i = 0 generate ls_cell : HA  port map (a(0), b(0), sum(0), c_in(1));end generate lsbit; middle_bit : if i 0 and i wid-1 generate middle_cell : FA  port map (a(i), b(i), c_in(i), sum(i), c_in(i+1));end generate middle_bit; ms_bit : if i = wid-1 generate ms_cell : FA  port map (a(i), b(i), c_in(i), sum(i), carry);end generate ms_bit; end generate adder; Agenda Generate Assert Function Overloading FILE IO Assert Definition [Label:] assert Condition [report StringExpression] [severity Expression]; Note The message is written when the Condition is False! The default string for report clause is “Assertion violation” The default string for severity clause is “ERROR” Concurrent Assertions Concurrent Procedure Calls Label : assert condition report error_string