数据库 ch6_3m.pptVIP

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Agenda Other Features in VHDL Generate Assert Function Overloading FILE IO Generate Example (1) ram32 : ram_0 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(7 downto 0)); ram_1 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(15 downto 8)); ram_2 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(23 downto 16)); ram_3 :sta