第十一章-半导体存储器解读.pptVIP

* * CMOS SRAM Analysis (Write) WL BL=1 V DD M 5 M 6 M 4 M 1 M 2 M 3 BL=0 Q=0 Q=1 * * 6T-SRAM — Layout VDD GND Q Q WL BL BL M1 M3 M4 M2 M5 M6 WL BL=1 V DD M 5 M 6 M 4 M 1 M 2 M 3 BL=0 Q=0 Q=1 * * Resistance-load SRAM Cell M 3 R L R L V DD WL Q Q M 1 M 2 M 4 BL BL * * SRAM Characteristics * * (2)差分灵敏放大器（用于SRAM） M 4 M 1 M 5 M 3 M 2 V DD bit bit SE y 偏置电流源 ISS 电流镜 I3 I4 I3=I4 OUT 稳态时，I1=I2=ISS/2 I1 I2 1.设bit下降到一个规定值时使得M1关断，则 I3=I4=0 I2=ISS OUT恒流放电至0 2.设bit下降到一个规定值时使得M2关断，则 I1=ISS I2=0 I3=I4=ISS OUT恒流充电至VDD * * 2. DRAM WWL BL 1 M 1 X M 3 M 2 C S BL 2 RWL V DD V DD - V T D V V DD - V T BL 2 BL 1 X RWL WWL (1) 3管DRAM单元 * * 3T-DRAM — Layout BL2 BL1 GND RWL WWL M3 M2 M1 WWL BL 1 M 1 X M 3 M 2 C S BL 2 RWL * * Write:通过字线和位线CS被充电或放电. Read: 电荷在存储电容和位线电容之间进行再分配 电压变化量较小; 典型值大约 250 mV. D V BL V PRE – (V BIT V PRE ) – C S C S C BL + ------------ = = V 破坏性读，需动态恢复刷新 (2) 1管DRAM单元 X 重分配后位线电压 CS上的初始电压 * * 1-T DRAM Cell Cross-section Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Layout * * （3）DRAM中的基于锁存器的灵敏电路 EQ V DD BL BL SE SE 存储1时BL大于存储0时相反 BL单元 在读或刷新时，产生一个虚拟的 BL 利用锁存器的正反馈将BL恢复到VDD或0 Vin Vout * * Open bitline architecture with dummy cells（位线断开结构） C S C S C S C S BLL L L 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE SE EQ Dummy cell Dummy cell （4）虚拟单元的产生 BL BL 1.刷新或读之前，EQ管导通，BL和 BL均为VDD/2， 同时选通Dummy cell ，充至VDD/2 2.刷新或读时，EQ管截止， L 1和L为高， BL维持VDD/2，BL高于或低于VDD/2 将位线分成左右两部分 * * 作业：P219 10.3 10.7 Only one select line active at a time. E.g., N= 10**6 = 2 **20 (1 Mword) means 1 million select signals By adding decoder reduce number of inputs from 1 million to 20 (address lines). Note, still have to generate 1 million select lines with a very biggggg decoder (see last lecture) Scheme on right, while reducing #inputs, leads to very tall and narrow memories (and very slow because of very long bit lines). Also very big (and slow) address decoder (good to t