[交通运输]嵌入式处理器架构与程式设计.pptVIP

嵌入式處理器架構與程式設計 王建民 中央研究院 資訊所 2008年 7月 Contents Introduction Computer Architecture ARM Architecture Development Tools GNU Development Tools ARM Instruction Set ARM Assembly Language ARM Assembly Programming GNU ARM ToolChain Interrupts and Monitor Lecture 10Interrupts and Monitor Outline Exception Handling and Software Interrupts ELF: Executable and Linking Format ARM Monitor and Program Loading Normal Program Flow vs. Exception Normally, programs execute sequentially (with a few branches to make life interesting) Normally, programs execute in user mode Exceptions and interrupts break the sequential flow of a program, jumping to architecturally-defined memory locations In ARM, SoftWare Interrupt (SWI) is the “system call” exception ARM Exceptions Types of ARM exceptions Reset: when CPU reset pin is asserted undefined instruction: when CPU tries to execute an undefined op-code software interrupt: when CPU executes the SWI instruction prefetch abort: when CPU tries to execute an instruction pre-fetched from an illegal address data abort: when data transfer instruction tries to read or write at an illegal address IRQ: when CPUs external interrupt request pin is asserted FIQ: when CPUs external fast interrupt request pin is asserted The Programmer’s Model Processor Modes (of interest) User: the “normal” program execution mode. IRQ: used for general-purpose interrupt handling. Supervisor: a protected mode for the operating system. The Register Set Registers R0-R15 + CPSR R13: Stack Pointer (by convention) R14: Link Register (hardwired) R15: Program Counter where bits 0:1 are ignored (hardwired) Terminology The terms exception and interrupt are often confused Exception usually refers to an internal CPU event floating point overflow MMU fault (e.g., page fault) trap (SWI) Interrupt usually refers to an external I/O event I/O device request reset In the ARM architecture manuals, the two terms are mixed together What do SWIs do? SWIs (often called software tra