[工学]Digital System Design.ppt

Digital System Design Example for IF (1/4) Good style takes advantage of if-else priority to synthesize correct logic module latch_if1(en,A,out); input en, A; output out; reg out; always @(en) begin if(en) out = A; end endmodule module code3(Sel , A , B1, B2); input Sel, [1:0]A; output [1:0] B1, B2; reg [1:0] B1,B2; always @ (Sel or A) if(Sel) if(A == 1) begin B1 = 0; B2 = 0; end else begin B1 = 1; B2 = 1; end else begin B1 = 2; B2 = 2; end endmodule Combinational Shifter (1/2) module SHIFTER (Sel, A,Y); input [1:0]Sel; input [5:0]A; output [5:0]Y; reg [5:0]Y; always@(Sel or A) begin case(Sel) 0: Y=A; 1: Y=A1; 2: Y=A1; default: Y=6b0; endcase end endmodule Combinational Shifter (2/2) module SHIFTER_SHIFTINOUT (Sel,ShiftLeftIn,ShiftRightIn,A,ShiftLeftOut,ShiftRightOut,Y); input [1:0]Sel; input ShiftLeftIn, ShiftRightIn; input [5:0]A; output [5:0]Y; output ShiftLeftOut,ShiftRightOut; reg ShiftLeftOut,ShiftRightOut; reg [5:0]Y; reg [7:0]A_Wide, Y_Wide; always@(Sel or ShiftLeftIn or ShiftRightIn or A) begin A_Wide={ShiftLeftIn,A,ShiftRightIn}; case(Sel) 0: Y_Wide = A_Wide; 1: Y_Wide = A_Wide1; 2: Y_Wide = A_Wide1; 3: Y_Wide = 8b0; endcase ShiftLeftOut = Y_Wide[7]; Y = Y_Wide[6:1]; ShiftRightOut = Y_Wide[0]; end endmodule SISO Shifter (1/4) module SISO_SR(clk, Clear, SI, SO); input clk, Clear, SI; output SO; reg [3:0] Reg4; always @(posedge clk or posedge Clear) begin if (Clear) Reg4 = 4b0; else begin Reg4[3] = Reg4[2]; Reg4[2] = Reg4[1]; Reg4[1] = Reg4[0]; Reg4[0] = SI; end end assign SO = Reg4[3]; endmodule SISO Shifter (2/4) SISO Shifter (3/4) module SISO_SR(clk, Clear, SI, SO); input clk, Clear, SI; output SO; reg [3:0] Reg4; always @(posedge clk or posedge Clear) begin : for_Local integer i; if (Clear) Reg4 = 4b0; else begin