X40上电时序.pptVIP

APWRG BPWRG In the block of A_PGS, the voltage of VCC3A is monitored by the internal analog comparator, each state is supplied to A_PGS output. The terminal is Open drain structure. 　The operation of detection is started when 3A_ON is equal to High. The analog Comparator has hysteresis voltage and generate highsignal when the following condition are satisfied. Greater than 2.943V(Typ.) at power on stage of VCC3A（Rising Edge）and lower than 2.793V (Typ.) at the shut down stage (Falling edge) In this period A_PGS is supplying H level. The Hysteresis Voltage are set 150mV +/- 50mV. At the High state, the delay time of 350ms +/- 10ms is set. APWRG BPWRG APWRG BPWRG 　In the block of B_PGS, the voltage of VCC5B and VCC3B are monitored by the internal analog comparator, each voltage state issupplied to B_PGS output. The terminal is Open drain structure. 　The operation of detection is started when both 5B_ON and 3B_ON are equal to High. The analog Comparator has hysteresis voltage and generate high signal when the following condition are satisfied. Greater than 4.461V(Typ.) at power on stage of VCC5M（Rising Edge）and lower than 4.311V (Typ.) at the shut down stage (Falling edge) after 47.5ms +/- 2.5ms Greater than 2.943V(Typ.) at power on stage of VCC3M（Rising Edge）and lower than 2.793V (Typ.) at the shut down stage (Falling edge) after 47.5ms +/- 2.5ms In this period B_PGS is supplying H level. The Hysteresis Voltage are set 150mV +/- 50mV. And at the High state, the delay time is set, when B_PGS become High, the delay time of 100ms +/- 5ms is set in case of A_PGS is equal to Low, and the delay time of 445ms +/- 5ms is set in case of A_PGS is equal to High. APWRG BPWRG BPWRG APWRG BPWRG Spec: From APWRG to BPWRG is 100+/-5ms VTT_PWRG VCCCPUCORE VR_PWRGD VCCCPUCORE VR_PWRGD by MAXIM 1907 VCCCPUCORE VR_PWRGD PCIRST# CC_CPUPWRGD Spec: From BPWRG to PCIRST# is 1ms GTL_CPURST# Spec: From PCIRST# to GTL_CPURST# is 1ms GTL_ADS# LPC_FRAME# P_TRDY# P_IRDY# P_FRAME# S0 TO