VHDL报告.docVIP

《EDA上机报告》 学院： 班级： 姓名： 学号： 2012年11月3日 试验一： 1.一位半加器（VHDL） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY half_add1 is PORT( A,B:IN STD_LOGIC; C,S:OUT STD_LOGIC ); END ENTITY HALF_ADD1; ARCHITECTURE ARCH OF HALF_ADDER1 IS begin S=A xor B; C=A and B; end arch; 2.半加器（原理图） 3.全加器（原理图） 4.全加器（例化语句） library ieee; use ieee.std_logic_1164.all; entity full_adder2 is port( A,B,Cin:in std_logic; Sum,Cout:out std_logic ); end full_adder2; architecture arch of full_adder is component half_adder1 port( A,B:in std_logic; S,C:out std_logic ); end component; component or22 port( A,B:in std_logic; S,C:out std_logic ); end component; signal x:std_logic_vector(0 to 2); begin ul:half_adder1 port map(A,B,X(0),x(1)); u2:half_adder1 port map(X(0),Cin,Sum,x(2)); u3:or22 port map(x(1),x(2),cout); end arch; 或门 library ieee; use ieee.std_logic_1164.all; entity or22 is port( A,B:in std_logic; C:out std_logic ); end or22; architecture arch of or22 is begin C=A or B; end arch; 实验二：四选一 1.IF….THEN….语句 library ieee; use ieee.std_logic_1164.all; entity Mux4_11 is port (A,B,C,D:in std_logic_vector(3 downto 0); Sel:in std_logic_vector(1 downto 0); Y:out std_logic_vector(3 downto 0) ); end Mux4_11; architecture arch of Mux4_11 is begin process (A,B,C,D,Sel) begin if (Sel=00) then Y = A; elsif (Sel=01) then Y = B; elsif (Sel=10) then Y = C; elsif (Sel=11) then Y = D; else NULL; end if; end process; end arch; 2.CASE….WHEN……语句 library ieee; use ieee.std_logic_1164.all; entity Mux4_12 is port (A,B,C,D:in std_logic_vector(3 downto 0); Sel:in std_logic_vector(1 downto 0); Y:out std_logic_vector(3 downto 0) ); end Mux4_12; architecture arch of Mux4_12 is begin process (A,B,C,D,Sel) begin case Sel is when 00 = Y = A; when 01 = Y