SoC设计方法与实现第八章_综合与STA教材教学课件.pptVIP

Example –.synopsys_dc.setup (tcl format) #/*.synopsys_dc.sretup */ #/*********************************************************/ set search_path [contact $search_path [list “.” “/usr/golden/library/std_cells”]] set target_library [list ex25_worst.db ex25_best.db] set link_library [list “*”,ex25_worst.db ex25_best.db] set symbol_library [list ex25.sdb] ? define_name_rules BORG –allowed “A-Za-z0-9” -first_restricted “_” \ -last_restricted “_” -max_length 30 \ -map [contact [list “\*cell\*” ”mycell”] [list “*-return” ”myreturn”]] set bus_naming_style {%s[%d]} set verilogout_no_tri true set verilogout_show_unconnected_pins true #/*For DFT: define scan style******/ set test_default_scan_style multiplexer_flip_flop Example of create_clock create_clock -name SYS_CLK -period 9 -waveform [list 0 4] [get_pins pll_clk] set_clock_uncertainty -setup 0.5 SYS_CLK set_clock_uncertainty -hold 0.5 SYS_CLK set_clock_latency 4 -min [get_clocks SYS_CLK] set_clock_latency 4.5 -max [get_clocks SYS_CLK] set_clock_transition 0.5 [get_clocks SYS_CLK] set_dont_touch_network [get_clocks SYS_CLK] Set_ideal_network [get_clocks SYS_CLK] Example of create_generated clock For a clk from a divider: create_generated_clock -divide_by 2 -source [get_pins pll_clk] -name 48MCLK [get_pins {crc/crm_clkc_clkgen/usb_clk}] set_clock_uncertainty -setup 0.5 48MCLK set_clock_uncertainty -hold 0.5 48MCLK set_clock_latency 4 -min [get_clocks 48MCLK] set_clock_latency 4.5 -max [get_clocks 48MCLK] set_clock_transition 0.5 [get_clocks 48MCLK] set_dont_touch_network [get_clocks 48MCLK] Set_ideal_network [get_clocks 48MCLK] Example - constraint.tcl #/****************************************/ #/*Clock specification and design constraints */ create_clock –period 33 –waveform [list 0 16.5] tck set_dont_touch_network [list tck trst] set_ideal_network [list tck trst] set_clock_latency 2.0 tck set_clock _uncertainty –setup 3.0 tck set_driveing_cell –lib_cell BUFF1X –pin Z [all_in