SoC设计方法与实现第十章_DFT教材教学课件.pptVIP

Steps of Scan Design Convert flip-flops (FF) to scan flip-flops (SFF) Connect SFF to scan chains In normal mode: SFF behave as usual In scan mode: SFF behave as shift register Scan Flip-Flop (SFF) Scan cell: Mux-D Scan Flip Flop type DFF SDFF The most widely accepted scan style Scan cell will cause larger area, larger setup time, more power consumption Scan Chain Connection Replace all FF with SFF Connect to scan chains Test Sequential Logic Using Scan SFFs scan chain help to initialize nodes and capture results – controllability observability Tools for Scan Synthesis and ATPG Fully supported by EDA tools Scan insertion DFT compiler from Synopsys DFT Advisor from Mentor Test vector generation (ATPG) TetraMAX from Synopsys FastScan from Mentor Test pattern verification STA is used to check the scan test timing in scan mode Simulation is used to verify ATPG pattern Scan Design Rules Scan design rules govern the controllability and observability of scan design (fault coverage) Scan design rule checking (DRC) provides you with feedback on the testability of your design (Does the signals can path the scan chain?) Basic Scan Design Rules Use only Mux-D type of flip-flops for all state variables All clocks/reset must be controlled from PIs. Clocks must not feed inputs of flip-flops (to D pin of FF) Do not use tri-state bus design or disable the tri-state buffer during scan test Example: Dealing with Tri-state bus Tri-state bus During scan shifts, multiple drivers on a bus may drive the bus simultaneously which causes bus contention problem or no driver on the bus lead to a floating bus. Fix: Mux added to make the bus controllable during scan mode Example: Dealing with Black Box Bypass Black Box Analog blocks, memories, hardmacros Example: Memory Block Interface Bypass Memory Block: adding shadow register (Optional) If the chip-testing goals include scan testing for AC coverage (transition and path delay), then the previous bypass method may not be