计算机组织结构chap12.pptVIP

William Stallings Computer Organization and Architecture Chapter 12 CPU Structure and Function Structure - The CPU CPU With Systems Bus Registers 用来参加运算, 服务于CPU. CPU must have some working space (temporary storage), called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy User Visible Registers General Purpose Data Address Condition Codes fig. 12.20 Example Register Organizations General Purpose Registers General purpose or specialized Data data registers or accumulator Addressing segment register Make them general purpose Increase flexibility and programmer options Increase instruction size complexity Make them specialized Smaller (faster) instructions Less flexibility How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC PowerPC User Visible Registers Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. JE --- Jump if zero May be in program status register fig. 12.3 Control Status Registers Program Counter PC Instruction Decoding Register IR Memory Address Register MAR Memory Buffer Register (MBR) MDR Program Status Word A set of bits PSW: Includes Condition Codes Sign of last result Zero Carry Equal Overflow Control bits Interrupt enable/disable Supervisor Other Registers May have registers pointing to: Process control blocks (PCB, see O/S) Interrupt Vectors (see O/S) N.B. CPU design and operating system design are closely linked Instruction Cycle (简化的指令执行过程) Revision: 取指, 执行 Stallings Chapter 3 Instruction Cycle (通常的指令执行过程) Fetch instructions Interpret instructions Calculate operand address Fetch operand Process data Write data Interrupt check Interrupt handle Indirect Cycle ADD $R1, (A) 在取操作数时, 若是间接寻址, 则需要更多的存储器访问 Can be thought of as additional instruction subcycle Instruction Cycle S