Last results obtained with the large GRPC prototype - IPNL - IN2P3随着大型GRPC原型IPNL - in2p3得到最后的结果.pptVIP
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Last results obtained with the large GRPC prototype - IPNL - IN2P3随着大型GRPC原型IPNL - in2p3得到最后的结果.ppt
kieffer@ipnl.in2p3.fr kieffer@ipnl.in2p3.fr An update on Power Pulsing with SDHCAL Kieffer Robert IPN Lyon ??CALICE collaboration meeting?? May 2011, CERN 21/05/11 kieffer@ipnl.in2p3.fr * Intro: SDHCAL Part I: The power pulsing with HARDROCs Part II: Beamtest under B field @ CERN Conclusion Outline 21/05/11 kieffer@ipnl.in2p3.fr * Absorber: 2 cm thick iron plates Each sensitive cassette contains a readout board stick to a GRPC. Total (barrel + end caps): 50 millions readout channels (1x1cm2) HARDROC power dissipation: 7.5 μW/channel (using power pulsing) =375 W for the whole SDHCAL very front end boards. Detector interface cards located on border sides host FPGAs: these cards will probably need active cooling or the use of specific power pulsed ASICs to operate data transfer tasks. SDHCAL 21/05/11 * kieffer@ipnl.in2p3.fr The readout board hosting 24 chips connected through a daisy chain scheme is controled by a DIF (detector interface) This board is fixed on a 50x33 cm2 GRPC detector. SDHCAL power pulsing test ASU The active sensitive unit: A non-magnetic metallic cassette contains this assembly. 21/05/11 DIF Redout board 1536 channels * kieffer@ipnl.in2p3.fr SDHCAL power pulsing principle 21/05/11 Readout architecture common to all calorimeters and minimization of data lines power Daisy chain using token ring mode Open collector, low voltage signals Low capacitance lines Acquisition DAQ IDLE MODE Chip 0 Chip 1 Acquisition DAQ IDLE MODE IDLE Chip 2 Acquisition IDLE MODE IDLE Chip 3 Acquisition IDLE MODE IDLE Chip 4 Acquisition IDLE MODE IDLE DAQ 1ms (.5%) .5ms (.25%) 1% duty cycle 99% duty cycle 198ms (99%) 5 events 3 events 0 event 1 event 0 event Chip 0 Chip 1 Chip 2 Chip 3 Chip 4 Data bus Courtesy : N.Seguin Moreau LAL * kieffer@ipnl.in2p3.fr Power Pulsing in HARDROC Shut down bias currents and reference voltages with vdd: ALWAYS ON Bandgap + other ref voltages + master I : POWER PULSED ON/OFF 3 Power pulsing lines used: Anlog, ADC, Digit
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