Combinational Logic - University of California, Berkeley：组合逻辑-加利福尼亚大学，伯克利.pptVIP

EECS 150 - Components and Design Techniques for Digital Systems Lec 05 – Boolean Logic9/4-04  David Culler Electrical Engineering and Computer Sciences University of California, Berkeley /~culler /~cs150 Review Design flow Design entry, High Level Analysis, Technology Mapping, Low-Level Analysis Role of Netlists and Hardware Description Languages Verilog Structural models Behavioral models Elements of the language Lots of examples Synchronous Sequential Circuits in Verilog module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q=D; endmodule // FF Seq. Circuit Behavior Other models Outline Review Motivation: working with combinational logic Truth Tables vs Boolean Expressions vs Gates Minimal Operators Boolean Algebra Manipulating Expressions and Circuits Proofs: Term rewriting Exhaustive Enumeration Simplifications De Morgan’s Law Duality Canonical and minimal forms (maybe) Combinational Logic (CL) Defined yi = fi(x0 , . . . . , xn-1), where x, y are {0,1}. Y is a function of only X. If we change X, Y will change immediately (well almost!). There is an implementation dependent delay from X to Y. CL Block Example #1 Truth Table Description: Boolean Equation: y0 = (x0 AND not(x1)) OR (not(x0) AND x1) y0 = x0x1 + x0x1 Gate Representation: More Complex gate: xor The example is the standard function called exclusive-or (XOR,EXOR) Has a standard algebraic symbol: And a standard gate symbol: CL Block Example #2 4-bit adder: R = A + B, c is carry out Truth Table Representation: 4-bit Adder Example Motivate the adder circuit design by hand addition: Add a0 and b0 as follows: Add a1 and b1 as follows: 4-bit Adder Example In general: ri = ai XOR bi XOR cin cout = aicin + aibi + bicin = cin(ai + bi) + aibi Now, the 4-bit adder: 4-bit Adder Example Graphical Representation of FA-cell ri = ai XOR bi XOR cin cout = aicin + aibi + bicin Alternative Implementation (with 2-input gate