Verilog_多功能数字钟设计源代码.docx

基本功能（1）以数字形式显示时、分、秒的时间；（2）小时计数器为同步24进制；（3）要求手动校时、校分。扩展功能（1）任意闹钟（2）小时为12/24进制可切换（3）报正点数（几点响几声）顶层模块ModuleTOP_clock (clk_50M,mode,JS,JF,hr_md,alarm_md,sec_dp,min_dp1,hour_dp1,min_dp2,hour_dp2,alarm);input clk_50M;input mode,JS,JF; //mode：校时模式选择开关，JS校时，JF校分input hr_md,alarm_md; //hr_md 12-24模式转换开关，alarm_md设定闹钟开关output [5:0]sec_dp;output [7:0]min_dp1;output [7:0]hour_dp1;output [7:0]min_dp2;output [7:0]hour_dp2;output alarm;wire [7:0]sec;wire [7:0]min;wire [7:0]hour;wire [7:0]chour;wire [3:0]min1;wire [3:0]hour1;wire [7:4]min2;wire [7:4]hour2;wire clk_1HZ;wire clk_1K;wire clk_500HZ;wireEN_sec; wireEN_min,EN_hr;wire EN_min1,EN_hr1;wire alarm1;wire [7:0]ala_min;wire [7:0]ala_hour;wire [7:0]ala_chour;wireala_EN_hr;wireEN_almin;wireEN_alhr;FP_1HZ FP1 (clk_50M,clk_1HZ);FP_1K FP2 (clk_50M,clk_1K);FP_500HZ FP3 (clk_50M,clk_500HZ);SEC TIME1 (clk_1HZ,1,EN_sec,sec,EN_min);MIN TIME2 (clk_1HZ,1,EN_min1,min,EN_hr);HOUR TIME3 (clk_1HZ,1,EN_hr1,hour);MIN TIME4 (clk_1HZ,1,EN_almin,ala_min,ala_EN_hr);HOUR TIME5 (clk_1HZ,1,EN_alhr,ala_hour);assignEN_almin=(alarm_md==1JF==1)?1:0;assignEN_alhr=(alarm_md==1JS==1)?1:0;assign ala_chour=(hr_md==1)?(((ala_hour[7:4]*10+ala_hour[3:0])==0|(ala_hour[7:4]*10+ala_hour[3:0])==12)?8{((ala_hour[7:4]*10+ala_hour[3:0])%12)/10,((ala_hour[7:4]*10+ala_hour[3:0])%12)%10}):ala_hour;assign EN_min1=(mode==1)?((JF==1)?1:0):EN_min;assign EN_hr1=(mode==1)?((JS==1)?1:0):EN_hr;assignEN_sec=(mode==1)?0:1;display dis1 (min1,min_dp1);display dis2 (min2,min_dp2);display dis3 (hour1,hour_dp1);display dis4 (hour2,hour_dp2);assignsec_dp=sec[7:4]*4b1010+sec[3:0]; //选择闹钟模式assign hour2=(alarm_md==1)?ala_chour[7:4]:chour[7:4];assign hour1=(alarm_md==1)?ala_chour[3:0]:chour[3:0];assign min2=(alarm_md==1)?ala_min[7:4]:min[7:4];assign min1=(alarm_md==1)?ala_min[3:0]:min[3:0];assign chour=(hr_md==1)?(((hour[7:4]*10+hour[3:0])==0|(hour[7:4]*10+hour[3:0])==12)?8{((hour[7:4]*10+hour[3:0])%12)/10,((hour[7:4]*10+hour[3:0])%12)%10}):hour;assign ala