计算结构POC报告04009028单佳炯.docVIP

The Report of POC Design NAME: Shan jiajiong(单佳炯） NUMBER:COURSE: COA Course Design PROJECT: POC Design DATE: MAR.28 2012 Purpose: The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation. Please refer to William ,Stallings.“Computer Organization and Architecture, Designing for Performance”,P.65~75; P.185~190. Tasks: a. The physical model of POC POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices). Figure  SEQ 图表 \* ARABIC 1 Printer Connection  REF _Ref155673830 \h \* MERGEFORMAT Figure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in  REF _Ref155673201 \h \* MERGEFORMAT Figure 2. Figure  SEQ 图表 \* ARABIC 2 The handshake-timing diagram between POC and the printer b. The logical model of POC The handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent). In order to ease your design work, the further explanations of the POC operations and some design hints are given as follows: The buffer register BR is used to hold a character that has been sent