EDA汇总 Verilog HDL编程.docVIP

【例4.8】BCD码加法器 module add4_bcd(cout,sum,ina,inb,cin); input cin;input[3:0] ina,inb; output[3:0] sum;reg [3:0] sum; output cout; reg cout; reg[4:0] temp; always @(ina,inb,cin) begin temp=ina+inb+cin; if(temp9) (cout,sum)=temp+6; else(cout,sum)=temp; end endmodule 【例4.10】带同步清0/同步置1（低电平有效）的D触发器 module dff_syn(q,qn,d,clk,set,reset); input d,clk,set,reset; output reg q,qn; always @(posedge clk) begin if(~reset) begin q=1’b0;qn=1’b1;end else if(~set) begin q=1’b1;qn=1’b0;end else begin q=d;qn=~d; end end endmodule 【例4.11】带异步清0/异步置1（低电平有效）的D触发器 module dff_asyn(q,qn,d,clk,set,reset); input d,clk,set,reset; output reg q,qn; always @(posedge clk or negedge set or negedge reset) begin if(~reset) begin q=1’b0;qn=1’b1;end else if(~set) begin q=1’b1;qn=1’b0;end else begin q=d;qn=~d; end end endmodule 【例4.13】4位计数器的仿真代码 `timescale 1ns/1ns `include “count4.v” module coun4_tp; reg clk,reset; wire[3:0] out; parameter DELY=100; count4 mycount(out,reset,clk); always #(DELY/2) clk=~clk; initial begin clk=0;reset=0; #DELY reset=1; #DELY reset=0; #(DELY*20) $finish; end initial $monitor($time,,”clk=%d reset=%d out=%d,clk,reset,out); endmodule 【例4.14】带同步复位的4位模10BCD码计数器 module count10(cout,qout,reset,clk); input reset,clk;output reg[3:0] qout;output cout; always @(posedge clk) begin if(reset) qout=0; else if(qout9) qout=qout+1; else qout=0; end assign cout=(qout==9)?1:0; endmodule 【例6.1】用case语句描述的4选1数据选择器 module mux4_1(out,in0,in1,in2,in3,se1); input in0,in1,in2,in3; input[1:0] se1; output reg out; always @(in0 or in1 or in2 or in3 or se1) case(se1) 2’b00: out=in0; 2’b01: out=in1; 2’b10: out=in2; 2’b11: out=in3; default:out=2’box; endcase endmodule 【例6.2】同步置数、同步清零的计数器 module count(out,data,load,reset,clk); input load,clk,reset; input[7:0] data;output reg[7:0] out; always @(posedge clk) begin if(!reset) out=8’h00; else if(load) out=data; else out=out+1; end endmodule 【例6.4】用initial过程语句对测试变量赋值 ’timescale 1ns/1ns module te