数字集成电路课程设计.pdfVIP

河海大学本科课程设计报告 摘 要 Verilog HDL 是一种硬件描述语言，是EDA 技术的重要组成部分。使用HDL 进行数字系统设计是电子设计技术的发展趋势和方向，因此学好这门知识并能够 灵活运用于课程设计是非常有必要也非常有意义的。 本次设计主要实现了一个任意分频器的简单功能。主要有以下两种方案: （一）对被分频时钟的上升沿和下降沿同时计数，计数到分频系数的一半时，对 输出时钟进行电平翻转，从而得到占空比为50%的分频时钟。 （二）对被分频时钟的上升沿和下降沿分别计数，得到一个上升沿分频时钟clk_p 和一个下降沿分频时钟clk_q，最后通过对这两个时钟进行相应的逻辑运 算，便可得到占空比为50%的输出时钟。 在仿真过程中，主要遇到的问题是无法综合。经讨论思考发现对同一时钟 的上升沿和下降沿同时进行操作时，Quartus II 将无法对这一行为进行综合。 最后，为解决综合的问题，我们对程序进行了必要的修改。最终，我们经过比较 选择了方案（二），实现了预期的目标。 【关键词】 Verilog HDL 任意分频器 半整数分频 综合 - 2 - 河海大学本科课程设计报告 ABSTRACT Verilog HDL is a hardware description language which is an important part of EDA technology. Nowadays,using HDL to design Digital systems is the development trend of electronic design technologies. So it is very necessary and very meaningful to learn this course and develop the ability to apply the knowledge learned to curriculum design flexibly. This design mainly realized a simple function of frequency divider at any frequency coefficients . Basically,we have the following two schemes: First: counting at the rise and fall of the input clock simultaneously, when arrive at half of the frequency coefficients, overturn the output clock, so a clock whose duty ratio is 50% can be achieved; Second: to get a clk_p at the rise of the input clock and a clk_q at the fall of the input clock respectively, then through the corresponding logic operation of the two clock,the wanted output clock can be easily achieved. In the debugging process, the main problem is unable to be synthesized. After discussion and reflection,we found that operations on one clock’s rise and fall at the same time are unable to be synthesized by Quartus II. Finally, in order to so