dvbs2标准下前向纠错码的编译码分析及fpga实现word格式论文.docx

is simulated using Matlab tool, LDPC code are then encoded with the Low complexity cyclic code encoding method, the problem of data overflow is overcomed in this process. The coding algorithm complexity is also verified from the aspects of the coding bit rate and the space of storage.Once again, several kinds of hard decision and soft-decision decoding algorithms are analized and compared, Fixed-point and quantizing、methods of optimizing the decoder parameters are introduced in decoding in order to improve the hardware complexity, anda simulation analysis is carried out with the aid of Matlab tools.Finally, BCH coding and LDPC encoding and decoding hardware implementation structures are proposed, Verilog HDL hardware description language is used to achieve the FPGA design for encoder and decoder with the help of QuartusII9.1 development platform and the Modelsim simulation tools. The simulation results and resource usage are obtained and are also compared with the Matlab software simulation results, themaximum frequency of encoder designed in this paper can reach more than 100M and that of decoder can reach more than 200M,but the resource utilization is low.Keywords: DVB-S2 standard; LDPC/ BCH code; Parallel encoder; reduced complexityMin-Sum decoding algorithm; Field Programmable Gate Arry目录摘要 .......................................................................................................................................................IABSTRACT .............................................................................................................................................III1 绪论 ..................................................................................................................................................11.1 数字通信系统及信道理论...................................................................................................11.1.1 数字通信系统....................................................................................................