非制冷红外焦平面阵列片上sigma-delta数字滤波器设计研究-design and research of sigma - delta digital filter on uncooled infrared focal plane array chip.docxVIP
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非制冷红外焦平面阵列片上sigma-delta数字滤波器设计研究-design and research of sigma - delta digital filter on uncooled infrared focal plane array chip
摘要摘要近年来,非制冷红外焦平面阵列在军用和民用领域越来越具有市场潜力,同 时成像系统从多功能模块集成向单片集成发展,因此片上集成 ADC 成为研究热点。 片上集成 ADC 不仅可以简化接口,还可以直接输出数字信号,避免模拟干扰,从 而提高系统性能。本文选择 Sigma-Delta ADC 作为片上 ADC 的结构,重点研究其中的数字滤波 器的设计。通过优化设计,降低数字滤波器的面积和功耗,进而提高 ADC 的性能。本文针对 2-1 级联 Sigma-Delta 调制器,设计了数字滤波器。其主要设计要求 包括:通带截止频率 20 KHz,最大通带波纹 0.001 dB,最小阻带衰减 85 dB,输出位宽 14 bit,输入速率 5.6448 MHz,输出速率 44.1 KHz,降采样率 128 倍。 设计中采用 Matlab、Synplify、Quartus II、Modelsim 等自动化设计软件联合设计,简化了设计过程的迭代;滤波器的实现采用多级级联方式,在保证性能的前 提下,减小硬件开销;在系统整合过程中,对设计进一步优化以增强系统的鲁棒 性。设计经过 Matlab 系统级设计与仿真验证,确定硬件结构;用 Verilog 硬件描述 语言进行设计,经过 Synplify、Quartus II 编译综合,最终得到寄存器传输级实现 以及门级映射;最后使用 Matlab、Modelsim 对整个系统联合测试验证。测试结果 表明,数字滤波器最大通带纹波 0.0009 dB,最小阻带衰减 85.21 dB,达到了设计 要求。关键词:非制冷红外焦平面阵列、读出电路、Sigma-Delta 模数转换器、数字滤波 器I -ABSTRACTABSTRACTIn recent years, uncooled infrared focal plane arrays are wildly used in the field of military and civilian, while imaging system is developed from integration of multi-function modules to monolithic, therefore on-chip ADC becomes a research focus. On-chip ADC can not only simplify the interface, but also avoid analog interference, which, as a result, improves system performance.Sigma-Delta ADC is selected as an on-chip unit while digital filter is the design focus. The digital filter is optimized in order to cut down chip area and power cost, so that the performance of ADC is improved.This dissertation presents an efficient design of digital filter, which can be used with the third order (2-1 cascaded) Sigma-Delta modulator. The circuit’s parameters are 20 KHz pass-band, 0.001 dB pass-band ripple, 85 dB stop band attenuation, 14-bit ENOB, 5.6448 MHz input speed, 44.1 KHz output speed and 128 oversampling ratio.Forward design approach is adopted. The co-design of softwares such as Matlab, Synplify, Quartus II and Modelsim, greatly simplify design process. Multi-stage cascade method is used, which guaranteeds system performance and reduces hardware overhead. Further optimization is taken in system integration process to enhance the robustness.Hardw
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