一种基于主极点补偿自适应电压调节电路设计-design of an adaptive voltage regulation circuit base on main pole compensation.docxVIP

摘 要随着集成电路技术的进步，工艺线宽越来越小，在同样的芯片面积下可以集 成越来越多的功能，芯片的功耗问题变得越来越突出。同时，随着集成电路的飞 速发展，诸如智能手机、平板电脑等移动设备的功能越来越多，体积越来越小， 在电池技术发展滞后的情况下，运用低功耗技术能够延长设备的使用时间。在众 多的低功耗技术中，自适应电压调节技术（Adaptive Voltage Scaling，AVS）可显 著降低负载能耗，从而越来越受到人们的重视。本文在分析了几种不同的电源管理技术之后，提出了一种基于主极点补偿的 AVS 电路，它利用环路中的一个加减双向计数模块产生的一个低频极点来使得环 路稳定，该计数模块通过控制数字脉宽调制器（Digital Pulse Width Modulator， DPWM）的输出占空比来调节输出电压。功率级电路基于转换效率较高的 Buck 拓 扑结构，采用同步整流方式进一步提高效率。本文在阐述了系统构成 及工作原理之后，着 重分析并设计了高线 性度的 DPWM 模块，该 DPWM 模块采用了延迟链加计数比较的混合式结构。在该模块 的设计中，提出了一种新颖的延迟链校准方式，按照特定的校准顺序对延迟链中 每一级延迟时间进行调整，较大程度地提高了其积分非线性（Integral nonlinearity， INL）。论文所设计 AVS 电路属于数模混合集成电路，通过数模混合设计和仿真流程，验证了系统功能的正确性，在不同的频率下电路能够自适应地调节出相应的电压。 电路输入电压为 2.7V-4.2V，输出电压为 0.9V-2.2V。所设计的电路最终在 CMOS 0.18μm 工艺下进行了流片，整个芯片的版图面积为 1300μm×1150μm。经过仿真分 析，相对于 DVS 技术，该 AVS 技术能节省最多 46%的能耗。关键词：低功耗，自适应电压调节，主极点，数字脉宽调制器ABSTRACTAs the integrated circuits technology developed fast in the last few years, more and more functions can be integrated into the same chip area, thus the power waste issue becomes serious. As to IC designers, it is impendency to develop low power ICs.At the other hand, the mobile device such as smart phones and flat computers are becoming smarter and smaller because of the development of IC, while the development of battery lags behind it.Fortunately, life span of the battery can be extended with the employment of low power design.Among all the low power designs, Adaptive Voltage Scaling(AVS)gets more and more attention, because it can sharply reduce total energy.In this thesis, a dominate-pole-based AVS is proposed after analysising several different power management technologies. A low frequency pole which is produced by a backward-forward counter in the loop makes the system stable. The output of the counter controls a Digital Pulse Width Modulator(DPWM), and thus the output voltage can be scaled. The high efficiency Buck converter which serves as it’s power stage works under synchronous rectification.In this thesis, a high linearity DPWM is proposed and designed. It is ba